Showing posts with label Dojo. Show all posts
Showing posts with label Dojo. Show all posts

Saturday, 31 October 2015

TDD with VHDL

We've recently been doing some interesting prospective work on FPGAs with VHDL and I thought it would be cool to try and update www.cyber-dojo.org to support the VHDL language.

Cyber Dojo has been our in-house training tool of choice for a long time now. It essentially enables you to practise programming the TDD way in a web-based environment. Multiple developers can join the same dojo session and we all review together at the end.

The first challenge was setting up a development envrionment for Cyber Dojo, which essentially meant getting a "Ruby on Rails" Linux server up and running. I chose to do this from scratch rather than paying for an image, so I went for the Manjaro distribution for a few reasons :

1. It's Arch based, and Arch is relatively lightweight
2. If we were using raw Arch it would be a pain the ass
3. I've used Manjaro before and it was relatively painless

After some fiddling around, I decided to use the command line of Passenger to create a development HTTP server using our forked cyber dojo code. Passenger can also run through Apache but it looked like a lot more of a faff.

All credit to my team member Pablo Mansanet who then found GHDL here :
http://home.gna.org/ghdl/

... and created the relevant docker files + other changes to Cyber Dojo to support the VHDL language.

We tried it internally (twice).... ironed out a couple of problems (largely related to renaming files)... pull-requested to Jon Jagger.... and wham! VHDL is now supported by Cyber Dojo :)


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity hiker_testbench is
end hiker_testbench;

architecture test_fixture of hiker_testbench is
   signal meaning_of_life_test : std_logic_vector (7 downto 0);
begin
   UUT: entity work.hiker port map (meaning_of_life_test);

   process
   begin
       wait for 1 ns; -- Signal propagation
       assert (meaning_of_life_test = "00101010") -- 42
               report "Meaning of life value incorrect"
               severity failure;
      
       assert false report "End of test" severity note;
       wait;
   end process;
end test_fixture;


If you fancy a more appropriate challenge than the existing exercises, we implemented a "half adder" as a test exercise which didn't stretch any of our less VHDL-savvy developers too badly (and also provided a base for a full adder so the guys who have more experience could leap ahead).

https://en.wikipedia.org/wiki/Adder_(electronics)

Enjoy! :)